1. Field of the Invention
The present invention relates to a surface acoustic wave filter of multi-stage connection type. More particularly, the present invention relates to a surface acoustic wave filter in which a plurality of surface acoustic wave filters are connected in a multi-stage connection (cascade connection).
2. Description of the Related Arts
Surface acoustic wave filters are gaining popularity as a filter for a transmitting/receiving circuit of a small communication apparatus such as a portable phone.
A surface acoustic wave filter, especially resonator type surface acoustic wave filter is formed of an electrode pattern formed on a piezoelectric substrate, including an interdigital transducer (hereafter referred to as IDT) and reflectors disposed on both sides of the IDT. A surface acoustic wave is excited inside of this electrode pattern. Also, a surface acoustic wave filter of multi-stage connection type is proposed in which a plurality of surface acoustic wave filters are serially connected.
FIG. 12 shows a construction of a conventional surface acoustic wave filter of multi-stage connection type. This filter includes a plurality of surface acoustic wave filters (109, 110) of transversal coupling type connected serially via a metal electrode film (cascade connection section 102).
Generally, IDT 107 includes an excitation section formed of a plurality of electrode fingers as well as a terminal-side bus bar 103 and a connection-side bus bar 104 disposed on upper and lower sides of the IDT. As an example of IDT in the surface acoustic wave filter, there has been developed a filter such that a line width of an electrode finger and an interval between electrode fingers are each 3.2 .mu.m; an electrode period .lambda. of IDT is 12.8 .mu.m; a width of a terminal-side bus bar 103 and a connection-side bus bar 104 along an up-and-down direction of the drawing is about 15.lambda..
FIG. 13 is a circuit block diagram of the surface acoustic wave filter shown in FIG. 12. A filter chip 113 of FIG. 13 corresponds to the surface acoustic wave filter formed on a piezoelectric substrate 100 of FIG. 12. Generally, matching circuits 111, 112 are attached to an input side and an output side of the filter chip 113 for providing an impedance matching with an external circuit. Also, in such a surface acoustic wave filter including connection via the cascade connection section 102, an impedance mismatching often occurs also at the cascade connection section 102, causing an extremely great loss at that section.
Therefore, an external circuit (an inductor L in the drawing) as shown in FIGS. 12 and 13 is added to provide an impedance matching at the cascade connection section 102. For this external circuit, various kinds of circuits are proposed (Japanese Unexamined Patent Publication Nos. Hei 5(1993)-129884, Hei 6(1994)-276046, Hei 6(1994)-310978, Hei 7(1995)-7369, Hei 7(1995)-22891, Hei 7(1995)-22892).
However, the proposed matching circuits are accompanied by a drawback that the cost of the entire filter rises due to an increased area of the filter including this external circuit and the increased number of circuit elements, since the matching circuit is attached to an outside of the filter chip.
Here, the impedance mismatching in the cascade connection section 102 is caused by a capacitance component included in parallel with an input impedance and an output impedance of each surface acoustic wave filter. The capacitance component is, for example, a "parasitic capacitance" existing in each surface acoustic wave filter.
FIG. 14 is a view for explaining the parasitic capacitance at the IDT portion of the surface acoustic wave filter. The IDT includes an electrode finger section disposed at its center portion and bus bars 115 disposed on both sides of the electrode finger section. The electrode finger section includes a plurality of electrode fingers meshing with each other in a lattice-like configuration. The IDT is formed on a piezoelectric substrate 100 and is electrically insulated from a bottom 114 of the filter chip package.
Now, it is believed that the parasitic capacitance exists in portions 116 and 117 enclosed by ellipses as shown in FIG. 14. In other words, one parasitic capacitance (117) is a capacitance of a plate capacitor formed between the bus bar 115 of IDT and the bottom 114 of the package; and the other capacitance (116) is a capacitance existing in the vicinity of a tip of each electrode finger in the electrode finger section of IDT and a connecting portion of an electrode finger adjacent the tip with the bus bar 115. The impedance mismatching at the cascade connection section 102 will be reduced if this parasitic capacitance decreases.